Union electronics and information technology minister Ashwini Vaishnaw announced plans to scale the Design Linked Incentive (DLI) scheme to at least 50 fabless semiconductor companies in its next phase, up from the current 24 chip-design firms. Speaking at an interaction with DLI-supported companies in New Delhi on January 27, Vaishnaw highlighted the scheme's success, noting that 14 startups have secured funding worth ₹430 crore from venture capitalists since the programme's launch in 2022. The DLI scheme has facilitated 16 startup tape-outs, resulting in six chips fabricated at advanced nodes as small as 12nm, demonstrating tangible progress in India's semiconductor design ecosystem. According to the minister, "These outcomes validate our ecosystem-driven approach," emphasizing that India's semiconductor strategy was designed as a multi-year national mission rather than isolated incentives.
As part of the upcoming Semicon 2.0 programme, India has set ambitious targets for 3nm chip manufacturing by 2032 and 2nm technology by early 2030s. Vaishnaw stated that by 2029, India will have major capability for manufacturing and designing chips required in 70-75% of applications in the country. The minister emphasized that reaching 3nm and 2nm manufacturing would be a core pillar of Semicon 2.0, drawing lessons from how South Korea, Taiwan and Japan built their chip ecosystems. According to Vaishnaw, "By 2035, we should be among the top four semiconductor nations in the world." This aggressive timeline positions India against established global leaders like Taiwan's TSMC and South Korea's Samsung, which currently dominate advanced chip production with decades of experience and substantial R&D investment.
The government has provided advanced EDA tools resulting in nearly 2.25 crore tool-hours of usage, with 67,000 students and over 1,000 startup engineers actively engaged. On the manufacturing infrastructure front, the Dholera fab will handle 28 nanometer to 90 nm technology while SCL operates on 180 nm technology, together covering 75-80% of chips manufactured globally within the next 2-3 years. Vaishnaw indicated that tape-out facilities for mature nodes such as 180 nm would be anchored at SCL Mohali, while nodes down to 28 nm would be supported through the upcoming Tata fab in Dholera. Talent development has outpaced targets, with over 67,000 semiconductor professionals trained in just four years across 315 academic institutions against a 10-year goal of 85,000 skilled professionals.
Under Semicon 2.0, the government will concentrate support around six core chip categories: compute, RF, networking, power management, sensors and memory. According to Vaishnaw, "With these six, we can build any major system — whether it is defence, missiles, railways or automobiles." DLI-backed companies are designing chips across a wide technology spectrum, including indigenous SoCs and ASICs for surveillance, networking and embedded systems, RISC-V based processors and accelerators, AI-enabled low-power chips for IoT and edge applications, and telecom and wireless chipsets. The design push has translated into tangible outputs with 122 academic designs taped out, 56 chips fabricated at 180 nm at SCL Mohali, and 85 patents filed (75 by academia, 10 by startups).
Sharing feedback from recent global engagements, including the World Economic Forum in Davos, Vaishnaw noted that global industry sentiment has shifted sharply from scepticism in 2022 to active partnership interest today. The minister announced that the government will institute Deep Tech Awards in 2026 across sectors such as semiconductors, AI, space and biotech, with the first awards expected later this year. The SCL Mohali facility modernization is planned over three years with an investment of ₹4,500 crore to upgrade from its current outdated 180-nm technology. Projections indicate India's semiconductor market could reach $60-70 billion by 2026-2027, with the government's substantial incentives designed to attract billions in investment and foster a robust domestic ecosystem.
