IBM has unveiled a revolutionary chip architecture that can integrate nearly 100 billion transistors onto a chip approximately the size of a human fingernail. According to reports, this represents almost double the transistor density achieved by IBM's previous-generation technology. The company has referred to this breakthrough as the world's first sub-1 nanometer chip technology, though it's important to note that physical features smaller than one nanometer are currently untenable due to fundamental physical constraints. IBM's new sub-1 nm chip packs nearly 100 billion transistors onto a chip the size of a fingernail, nearly twice the density of IBM's 2 nm chip, unveiled in 2021. Enabled by a series of structural and material innovations, including IBM's groundbreaking three-dimensional nanostack architecture, the technology demonstrates how continued gains in performance and efficiency remain possible even as chip features approach atomic dimensions. The breakthrough depends on a new architecture IBM is calling "nanostack," what it says is the industry's first three-dimensional nanosheet-based transistor design. Very simply, rather than continuing to shrink transistors across a flat plane, IBM vertically stacked and staggered them, using 3D sequential integration to pack more computing into the same footprint.
The breakthrough technology utilizes IBM's new nanostack architecture, which employs a vertically stacked, staggered transistor design to significantly increase transistor density within the same chip footprint. As reported, this architecture builds on the company's earlier work on nanosheet transistors, which formed the foundation of IBM's 2-nanometer chip technology unveiled in 2021. The nanostack design vertically stacks and staggers transistors, taking advantage of 3D sequential integration to pack more transistors onto a chip. The design also unlocks the use of different material combinations within each stacked layer, optimizing performance and power efficiency of each transistor independent of the other. IBM's nanostack architecture was experimentally validated through ultra-thin dielectric bonding in CMOS integration, demonstration of dual-channel engineering capability, and functional CMOS inverter operation with expected switching performance. This represents what IBM characterizes as the first time in the semiconductor industry's 60-plus-year history that transistor scaling has been extended into the vertical, or Z, dimension. There's another benefit: because each layer is built separately, engineers can mix and match different materials in each one, tuning performance and power independently.
According to IBM's published technical reports, the nanostack architecture could deliver 50% higher computing performance or 70% more energy efficiency compared to the company's previous generation of 2-nanometer node chips. Jay Gambetta, IBM Fellow and Director of IBM Research, described the innovation as pointing to a future where computing power can increase substantially without a corresponding rise in energy consumption, calling it a major advance rather than an incremental improvement. In new research presented at VLSI 2026, IBM researchers demonstrated that the nanostack architecture provides 40 percent scaling in SRAM, unlocking the ability of chip designers to create much more efficient chips while also supporting the high-bandwidth data demands of advanced AI workloads. With this groundbreaking structure, logic technology can extend for the first time below the 1 nm node, advancing the era of angstrom-level scaling, where dimensions approach the size of individual atoms. The technology is described as generic — applicable to CPUs, GPUs, mobile chips, and AI accelerators with the expectation that application-specific customization will emerge as the design community engages with it. "With our new nanostack architecture, we're not just making smaller transistors, we're reinventing how chips are built to deliver dramatically more power and energy efficiency," said Gambetta, calling it "a landmark moment in computing, pushing technology beyond the nanometer era to the scale of atoms."
Both Gambetta and Bu emphasized AI infrastructure as a primary application context for the new technology. The 40% SRAM scaling gain is particularly significant for AI accelerator design, where on-chip memory capacity and bandwidth are persistent bottlenecks. Bu indicated plans to discuss design implications at DAC (Design Automation Conference) this year. "Think about AI computing — everyone demands more performance, but no one wants to pay the power bill," Bu said. "This new innovation will deliver 50% higher performance compared to what's the best available chip today, and at the same time it can reduce power by 70% if you choose to manage your power budget — which is a very critical component for AI." The technology's ability to deliver both higher performance and reduced power consumption makes it particularly valuable for AI workloads that require massive computational power while maintaining energy efficiency. The promised efficiency gain matters significantly as the generative-AI boom has turned chip power consumption into one of the computing industry's biggest problems, with data centers straining grids and hunting for water for cooling. A chip that does the same work for 70% less energy will help address both power consumption and cooling challenges. IBM currently conducts this research at its semiconductor facility in Albany, New York, in collaboration with partners including Rapidus, the Japanese foundry working to bring IBM's 2 nm nanosheet technology into production.
With the expectation of the earliest adoption of nanostack technology at the sub-1 nm node, IBM sees a path to production in as early as the next 5 years. The nanostack architecture was developed through collaboration with IBM and partners including Lam Research Corp. (Nasdaq: LRCX), Tokyo Electron (TEL), and SCREEN Semiconductor Solutions, Ltd., who have been working together to develop new High NA EUV processes and tools that have already yielded working devices. IBM and its partners conduct this work at a leading semiconductor research facility in Albany, New York, which will soon be home to a High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography tool, essential for the future of logic scaling. With the new nanostack architecture, IBM's semiconductor roadmap projects at least a decade of future scaling, representing the latest testament to IBM as a leader in semiconductor R&D. IBM declined to specify how NanoStack technology will be licensed or transferred to manufacturing partners, stating that the focus at present is on helping Rapidus successfully establish 2 nm manufacturing capability. At this point the sub-1 nm chip is a research achievement, not a shipping product, but if IBM achieves production within five years or sooner, this technology is likely to be a significant and profitable product.
