The ₹1.27 trillion Semicon 2.0 scheme received a comprehensive overhaul on August 31, 2025, introducing significant improvements over the previous design-linked incentive (DLI) scheme. According to latest reports, the scheme now offers hybrid capital stack funding with seed funding up to ₹15 crore, followed by equity co-investment or royalty financing once startups have raised private venture capital. This represents a fundamental shift from the earlier reimbursement model, providing startups with grant, equity and royalty options instead of a single reimbursement route - a structure better suited to an industry where products can take five years to reach the market. The government has also dropped the numeric cap on foreign shareholding, replacing it with a qualitative requirement that companies remain owned and controlled by Indian citizens or Overseas Citizens of India, while allowing Indian startups to bid in consortium mode with global companies.
The new Semicon 2.0 scheme introduces significant improvements over the previous design-linked incentive (DLI) scheme. As reported by Business Standard, for the first time, the government offers to co-invest with VCs if startups require funds beyond the earlier limit of ₹15 crore or 50% of eligible expenditure. The scheme also introduces royalty financing support, where the government provides lump sum funding to help companies launch products, with companies returning 5% royalty on net revenue from the product up to 1.5 times the financial support. The India Semiconductor Mission (ISM) now runs design as well as manufacturing, with design previously handled by the Centre for Development of Advanced Computing (C-DAC). The scheme also provides upfront capex support across manufacturing categories, mostly 30-40%, down from Semicon 1.0's uniform 50% support. Meity hopes this will help nurture over 100 fabless semiconductor companies, representing a fourfold increase in the total number of players.
Indian chip design startups face significant market challenges beyond funding constraints. According to Business Standard, Jaswinder Ahuja, former corporate vice president at Cadence Design Systems, emphasizes that startups need 'compelling products, not 'me-too' designs'. He notes that companies cannot expect buyers to switch from established vendors like Qualcomm, NXP, and ST Microelectronics without 10% efficiency improvements and proven track records. However, some market opportunities are emerging, particularly in CCTV cameras, where government restrictions on uncertified internet-connected cameras have created potential for over 2 million 'designed in India' chips per year. Ahmedabad-based IndieSemiC is targeting 5% market share initially with plans to reach 20%. The latest scheme addresses these challenges by providing graded support at 35% upfront capital for advanced 2.5D and 3D packaging against 25% for legacy work, playing to India's comparative advantage where nine assembly and testing plants are already approved under Semicon 1.0.
Despite government support, several industry stakeholders have raised concerns about the new scheme. Neil Shah of Counterpoint Research highlights the 'clash between government control and global deep-tech market realities', particularly the requirement for CDAC co-ownership of intellectual property. He warns that this could alienate top global venture capital and limit growth opportunities. Ravi Jain of TDK Ventures notes that global captives are offering 'golden handcuffs' to young techies, making it difficult for startups to attract talent. The lack of ecosystem infrastructure remains a critical challenge, as evidenced by c2i Semiconductors'* sale to Infineon within less than two years due to the absence of specialized testing facilities and global buyer relationships. The latest scheme addresses infrastructure concerns by providing up to 75% funding for both capital grants and operating budgets for public labs, fixing a structural gap where labs historically received capital grants but no operating budgets.
The success of Semicon 2.0 will be crucial for India's broader semiconductor ambitions. As reported by Business Standard, without a vibrant homegrown chip design ecosystem, India's goal of becoming a top-five global semiconductor player will remain challenging. The scheme represents a significant government commitment to push the chip design agenda forward, though it faces the challenge of balancing domestic control with global market realities. Industry experts suggest the scheme could substantially derisk investments and drive up company valuations across the semiconductor value chain, from innovation to capacity building. However, the largest risk remains the administrative load - ISM now runs the entire value chain, ten categories, equity management, royalty tracking, and investment decisions. Whether it works will depend on a step-jump in the capacity of the ministry and ISM to govern this complex mission. The scheme's hybrid capital stack approach addresses the previous scheme's limitations, where only 24 of a target of 100 firms received fiscal support due to the five-year gestation periods that didn't match the reimbursement model.
